--600 Second Street NE --Hopkins, MN 55343-8384
May 1999 to Present (active account)
Gerneral Processing Unit (GPU) for the Multiple
Launched Rocket System (MLRS)
Specify, architect and design the GPU for MLRS.
Design consits of embedded Power PC 603e processor operating at
128MHZ (internal)/32 MHZ BUS, 64 bit data BUS, 32 Mbytes Synch
DRAM, 32 Mbytes Flash.
All assembly glue logic and difital interfaces are incorproated
in a single XILINX vertex FPGA ( >1.2 Million gates).
All FPGA logic captured in VHDL.
FPGA interfaces include: six (6) programmable ( >2Mb/s) baud
rate, I/O FI-FO buffered, asynchronous UARTS; 12 Bit A/D interface;
two (2) programmable SDLCs; SDRAM 62 bit EDAC; 10 Base T Ethernet
interface; 16/16 parallel I/O; SDRAM, Flash interface; four (4)
special MLRS equipment interfaces; ETC.