July 1988 to January 1999

Processing Interface for Low Resolution Infrared Video Sensor for Night Vision Application

Tasks Involved:

• Interface Mechanized in single XILINX FPGA.
• Data Flow, Pipelined, DSP Functions Mechanized in FPGA
• High Speed Concurrent Processing, 60 Frames per second interleaved.
• Gate level mechanized "Bad Pixel Replacement" and "Smoothing Function" (expand 160 pixels/line X 120 lines to 640 pixels/line X 480 lines) algorithms.